code: plan9front

Download patch

ref: 00328b5759f66400aed0e71ccc687250113e61ee
parent: 9b0efa4176aa9437160c7970f3637e33f8196fce
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Sun Jun 28 14:22:36 EDT 2015 

pc, pc64: toggle bit 2 in port 0x61 to reset and enable PCI SERR# nmi's, print nmi status


--- a/sys/src/9/pc/trap.c
+++ b/sys/src/9/pc/trap.c
@@ -175,7 +175,7 @@
 	outb(0x70, 0);
 
 	x = inb(0x61) & 0x07;		/* Enable NMI */
-	outb(0x61, 0x08|x);
+	outb(0x61, 0x0C|x);
 	outb(0x61, x);
 }
 
@@ -422,7 +422,8 @@
 			 * Don't re-enable, it confuses the crash dumps.
 			nmienable();
 			 */
-			iprint("cpu%d: PC %#8.8lux\n", m->machno, ureg->pc);
+			iprint("cpu%d: nmi PC %#8.8lux, status %ux\n",
+				m->machno, ureg->pc, inb(0x61));
 			while(m->machno != 0)
 				;
 		}
--- a/sys/src/9/pc64/trap.c
+++ b/sys/src/9/pc64/trap.c
@@ -175,7 +175,7 @@
 	outb(0x70, 0);
 
 	x = inb(0x61) & 0x07;		/* Enable NMI */
-	outb(0x61, 0x08|x);
+	outb(0x61, 0x0C|x);
 	outb(0x61, x);
 }
 
@@ -416,7 +416,8 @@
 			 * Don't re-enable, it confuses the crash dumps.
 			nmienable();
 			 */
-			iprint("cpu%d: PC %#p\n", m->machno, ureg->pc);
+			iprint("cpu%d: nmi PC %#p, status %ux\n",
+				m->machno, ureg->pc, inb(0x61));
 			while(m->machno != 0)
 				;
 		}