shithub: plan9front

Download patch

ref: 04d1e6ffe92da311d1dd6463dfa347ad7db14c2d
parent: fe033ae81611a7a98d51b38ca5a8e9bc5638b996
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Mon Jun 13 19:24:14 EDT 2022

imx8/gpio: allow 0 as "no-op" gpio pin

as the gpio controller number starts at 1,
we can use 0 to mean "no pin", so passing
0 to gpioout() or gpioin() pin argument
will have no effect.

--- a/sys/src/9/imx8/fns.h	Mon Jun 13 19:00:06 2022
+++ b/sys/src/9/imx8/fns.h	Mon Jun 13 19:24:14 2022
@@ -156,6 +156,6 @@
 extern uint iomuxgpr(int gpr, uint set, uint mask);
 
 /* gpio */
-#define GPIO_PIN(n, m)	(((n)-1)<<5 | (m))
+#define GPIO_PIN(n, m)	((n)<<5 | (m))
 extern void gpioout(uint pin, int set);
 extern int gpioin(uint pin);
--- a/sys/src/9/imx8/gpio.c	Mon Jun 13 19:00:06 2022
+++ b/sys/src/9/imx8/gpio.c	Mon Jun 13 19:24:14 2022
@@ -38,17 +38,19 @@
 static Ctlr*
 enable(uint pin)
 {
-	Ctlr *ctlr = &ctlrs[pin/32];
+	Ctlr *ctlr;
 
-	assert(ctlr < &ctlrs[nelem(ctlrs)]);
+	pin /= 32;
+	if(pin < 1 || pin > nelem(ctlrs))
+		return nil;
 
+	ctlr = &ctlrs[pin-1];
 	if(!ctlr->enabled){
 		setclkgate(ctlr->clk, 1);
 		ctlr->reg[GPIO_IMR] = 0;
 		ctlr->dir = ctlr->reg[GPIO_GDIR];
 		ctlr->enabled = 1;
 	}
-
 	return ctlr;
 }
 
@@ -57,7 +59,8 @@
 {
 	int bit = 1 << (pin % 32);
 	Ctlr *ctlr = enable(pin);
-
+	if(ctlr == nil)
+		return;
 	if((ctlr->dir & bit) == 0)
 		ctlr->reg[GPIO_GDIR] = ctlr->dir |= bit;
 	if(set)
@@ -71,7 +74,8 @@
 {
 	int bit = 1 << (pin % 32);
 	Ctlr *ctlr = enable(pin);
-
+	if(ctlr == nil)
+		return -1;
 	if(ctlr->dir & bit)
 		ctlr->reg[GPIO_GDIR] = ctlr->dir &= ~bit;
 	return (ctlr->reg[GPIO_DR] & bit) != 0;