shithub: plan9front

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ref: 15b903c4e187b82d6dd01b8284b244945522c06d
parent: 18b3847aef8428503b8889b3a986d38e5e6ed584
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Wed May 12 16:40:51 EDT 2021

pc64: avoid getcr3() in mmuflushtlb()

it turns out that calculating physical address of pml4 is faster
than reading the machine register, so pass it explicitely.

--- a/sys/src/9/pc64/fns.h	Wed May 12 16:24:36 2021
+++ b/sys/src/9/pc64/fns.h	Wed May 12 16:40:51 2021
@@ -96,7 +96,7 @@
 void	meminit0(void);
 void	memreserve(uintptr, uintptr);
 void	mfence(void);
-#define mmuflushtlb() putcr3(getcr3())
+#define mmuflushtlb(pml4) putcr3(pml4)
 void	mmuinit(void);
 uintptr	*mmuwalk(uintptr*, uintptr, int, int);
 char*	mtrr(uvlong, uvlong, char *);
--- a/sys/src/9/pc64/main.c	Wed May 12 16:24:36 2021
+++ b/sys/src/9/pc64/main.c	Wed May 12 16:40:51 2021
@@ -239,7 +239,7 @@
 	if((pte = mmuwalk(m->pml4, REBOOTADDR, 0, 0)) != nil)
 		*pte &= ~PTENOEXEC;
 
-	mmuflushtlb();
+	mmuflushtlb(PADDR(m->pml4));
 
 	/* setup reboot trampoline function */
 	f = (void*)REBOOTADDR;
@@ -350,5 +350,5 @@
 	 * You might think it would be a win not to do this in that case,
 	 * especially on VMware, but it turns out not to matter.
 	 */
-	mmuflushtlb();
+	mmuflushtlb(PADDR(m->pml4));
 }
--- a/sys/src/9/pc64/mmu.c	Wed May 12 16:24:36 2021
+++ b/sys/src/9/pc64/mmu.c	Wed May 12 16:40:51 2021
@@ -67,7 +67,7 @@
 	tss->rsp1[1] = stack >> 32;
 	tss->rsp2[0] = (u32int)stack;
 	tss->rsp2[1] = stack >> 32;
-	mmuflushtlb();
+	mmuflushtlb(PADDR(m->pml4));
 }
 
 static void kernelro(void);