shithub: plan9front

Download patch

ref: 34dab15f408e8c272af406010b2bc6e5f7b1c473
parent: 739e15c17839ae1bf03f9a27ed170f3bcb280430
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Sun Jul 10 09:03:55 EDT 2022

imx8: reset lcdif and sn65sdi86 bridge before init

--- a/sys/src/9/imx8/lcd.c	Sun Jul 10 08:54:09 2022
+++ b/sys/src/9/imx8/lcd.c	Sun Jul 10 09:03:55 2022
@@ -441,6 +441,14 @@
 }
 
 static void
+lcdifreset(void)
+{
+	wr(lcdif, LCDIF_CTRL_SET, CTRL_SFTRST);
+	delay(1);
+	wr(lcdif, LCDIF_CTRL_SET, CTRL_CLKGATE);
+}
+
+static void
 lcdifinit(struct video_mode *mode)
 {
 	wr(lcdif, LCDIF_CTRL_CLR, CTRL_SFTRST);
@@ -501,6 +509,11 @@
 {
 	int n;
 
+	// soft reset
+	i2cwritebyte(dev, 0x09, 1);
+	while(i2creadbyte(dev, 0x09) & 1)
+		;
+
 	// clock derived from dsi clock
 	switch(cfg->hs_clk/2000000){
 	case 384:
@@ -838,8 +851,10 @@
 	gpioout(GPIO_PIN(3, 20), 1);
 
 	bridge = i2cdev(i2cbus("i2c4"), 0x2C);
-	if(bridge == nil)
-		return;
+	if(bridge == nil){
+		err = "could not find bridge";
+		goto out;
+	}
 	bridge->subaddr = 1;
 
 	/* power on mipi dsi */
@@ -857,6 +872,8 @@
 	setclkrate("disp.rtrm_clk", "system_pll1_clk", 400*Mhz);
 	setclkgate("disp.axi_clk", 1);
 	setclkgate("sim_display.mainclk", 1);
+
+	lcdifreset();
 
 	setclkrate("mipi.core", "system_pll1_div3", 266*Mhz);
 	setclkrate("mipi.CLKREF", "system_pll2_clk", 25*Mhz);