code: plan9front

Download patch

ref: 74cc358c2cfb4c50954a35cbcbeec4e67889f030
parent: d20cf9ff42af7b08261caa1ba0356b66b76b9618
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Mon Feb 6 13:28:54 EST 2023

reform: move SAI iomux/clock initialization into probe()

--- a/sys/src/9/imx8/sai.c
+++ b/sys/src/9/imx8/sai.c
@@ -392,17 +392,6 @@
 	adev->status = saistatus;
 	adev->ctl = saictl;
 
-	intrenable(IRQsai2, saiinterrupt, ctlr, BUSUNKNOWN, "sai2");
-	ctlr->hp = gpioin(GPIO_PIN(4, 21));
-	gpiointrenable(GPIO_PIN(4, 21), GpioEdge, jacksense, ctlr);
-	saireset(ctlr);
-
-	return 0;
-}
-
-void
-sailink(void)
-{
 	iomuxpad("pad_sai2_rxfs", "gpio4_io21", "SION ~LVTTL HYS ~PUE ~ODE FAST 45_OHM");
 	iomuxpad("pad_sai2_rxc", "sai2_rx_bclk", "~LVTTL HYS PUE ~ODE FAST 45_OHM");
 	iomuxpad("pad_sai2_rxd0", "sai2_rx_data0", "~LVTTL HYS PUE ~ODE FAST 45_OHM");
@@ -414,5 +403,16 @@
 	setclkrate("sai2.ipg_clk", "audio_pll1_clk", 25*Mhz);
 	setclkgate("sai2.ipg_clk", 1);
 
+	intrenable(IRQsai2, saiinterrupt, ctlr, BUSUNKNOWN, "sai2");
+	ctlr->hp = gpioin(GPIO_PIN(4, 21));
+	gpiointrenable(GPIO_PIN(4, 21), GpioEdge, jacksense, ctlr);
+	saireset(ctlr);
+
+	return 0;
+}
+
+void
+sailink(void)
+{
 	addaudiocard("sai", saiprobe);
 }