shithub: plan9front

Download patch

ref: 80268af29eb1dfc1ca4fc528f70c5af17286dd2c
parent: a2baa8634834b462a613ff6cc74becee2efc9a3c
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Sun Nov 7 12:47:09 EST 2021

bcm64/sdhc: add *emmc2bus kernel parameter to set dma dram bus address

On the raspberry pi 4, depending on the chip revision,
the emmc2 controller has different dram bus address window,
so make it configurable.

--- a/sys/src/9/bcm64/sdhc.c	Sun Nov  7 12:43:36 2021
+++ b/sys/src/9/bcm64/sdhc.c	Sun Nov  7 12:47:09 2021
@@ -199,11 +199,11 @@
 
 struct Ctlr {
 	Rendez	r;
-	Rendez	cardr;
 	int	fastclock;
 	ulong	extclk;
 	int	appcmd;
 	Adma	*dma;
+	uintptr	busdram;
 };
 
 static Ctlr emmc;
@@ -247,7 +247,7 @@
 			p->desc |= len<<OLength | End | Int;
 		else
 			p->desc |= Maxdma<<OLength;
-		p->addr = dmaaddr((void*)a);
+		p->addr = emmc.busdram + (PADDR(a) - PHYSDRAM);
 		a += Maxdma;
 		len -= Maxdma;
 		n--;
@@ -293,7 +293,11 @@
 {
 	u32int *r;
 	ulong clk;
+	char *s;
 
+	emmc.busdram = soc.busdram;
+	if((s = getconf("*emmc2bus")) != nil)
+		emmc.busdram = strtoull(s, nil, 16);
 	clk = getclkrate(ClkEmmc2);
 	if(clk == 0){
 		clk = Extfreq;
@@ -401,9 +405,9 @@
 		WR(Interrupt, i);
 	}
 	WR(Cmdtm, c);
-	now = m->ticks;
+	now = MACHP(0)->ticks;
 	while(((i=r[Interrupt])&(Cmddone|Err)) == 0)
-		if(m->ticks-now > HZ)
+		if(MACHP(0)->ticks - now > HZ)
 			break;
 	if((i&(Cmddone|Err)) != Cmddone){
 		if((i&~(Err|Cardintr)) != Ctoerr)
@@ -507,7 +511,7 @@
 		cachedwbse(buf, len);
 	else
 		cachedwbinvse(buf, len);
-	WR(Dmadesc, dmaaddr(emmc.dma));
+	WR(Dmadesc, emmc.busdram + (PADDR(emmc.dma) - PHYSDRAM));
 	okay(1);
 }
 
@@ -549,8 +553,6 @@
 	i = r[Interrupt];
 	if(i&(Datadone|Err))
 		wakeup(&emmc.r);
-	if(i&Cardintr)
-		wakeup(&emmc.cardr);
 	WR(Irpten, r[Irpten] & ~i);
 }