ref: 6dbebb2b4b262f0ab78f1202cc97805401ae298e
parent: 2a725ccf44da1b8460834dd4e239ea58e4693595
author: 9ferno <gophone2015@gmail.com>
date: Sat Oct 16 07:38:10 EDT 2021
fine tuned memory locations
--- a/os/pc64/l.s
+++ b/os/pc64/l.s
@@ -135,6 +135,9 @@
CLD
REP; STOSL
+ /*
+ * map from KZERO = 0 to KTZERO using 4096 pages
+ */
MOVL $PML4ADDR, SI
MOVL SI, AX /* PML4 */
MOVL AX, DX
@@ -146,7 +149,18 @@
MOVL DX, (AX) /* PDPE for KZERO = 0 */
/*
- * map from KZERO = 0 to KTZERO using 4096 pages
+ * fill from PT0ADDR to KTZERO with page tables
+ * KTZERO 2MiB - PT0ADDR 0x116000 = 0xea000 = 958 464 bytes
+ * available memory 0xea000 / PTSZ 0x1000 = 0xea = 234 page tables
+ * Hence, 234 entries in the PD table
+ * CX = 234 for this loop
+ * If CX > 512, then we need more PD tables.
+ * At the lowest level of granularity, each page table maps 2MiB
+ * With 234 PDE's, we are building page tables for
+ * 234 * 2MiB = 468MiB of memory
+ * This amount of memory should get us through booting until
+ * meminit() maps the rest of the memory using the
+ * e820 memory map.
*/
ADDL $PTSZ, AX /* PD0 at PML4 + 2*PTSZ */
ADDL $PTSZ, DX /* PT0 at PML4 + 3*PTSZ */
@@ -161,6 +175,10 @@
MOVL $(PT0ADDR), AX
MOVL $(PTEWRITE|PTEVALID), DX
+ /* each PTE uses 8 bytes => (>>3).
+ * As many PTE's as possible until KTZERO.
+ * With each PTE mapping 1 page (0x1000 = 4096 bytes).
+ */
MOVL $((KTZERO-PT0ADDR)>>3), CX
pteloop:
MOVL DX, (AX) /* PTE from 0 */
--- a/os/pc64/mem.h
+++ b/os/pc64/mem.h
@@ -57,6 +57,11 @@
/*
* Fundamental addresses
*/
+ /* free conventional memory starts from 0x500 as per the
+ * BIOS memory map
+ * But, using 0x1200ull to be in sync with 9front source built 9boot*
+ * executables
+ */
#define CONFADDR (0x1200ull) /* info passed from boot loader */
/* Both these should be below 1MiB as they are addressed from real
* mode which can address only upto 1MiB.
@@ -63,37 +68,40 @@
* check the e820 memory map to figure out the availble memory below
* 1MiB
* The intel manual mentions a 4KiB (0x1000) page for ap bootstrap code
+ * sync these values in os/pc64/mkfile too
*/
-#define REBOOTADDR (0x4000ull) /* reboot code - physical address */
-#define APBOOTSTRAP (0x5000ull) /* Application Processor (AP) bootstrap code */
-#define IDTADDR (KDZERO+0x10000ull) /* idt */
-#define GDTADDR (KDZERO+0x11000ull) /* gdt */
-#define CPU0MACH (KDZERO+0x12000ull) /* Mach for bootstrap processor (BSP) */
-#define CPU0END (KDZERO+0x22000ull) /* CPU0MACH + (MACHSIZE = 64 KiB = 0x10 000) */
+#define REBOOTADDR (0x2000ull) /* reboot code - physical address */
+#define APBOOTSTRAP (0x3000ull) /* Application Processor (AP) bootstrap code */
+
+#define IDTADDR (KDZERO+0x0ull) /* idt */
+#define GDTADDR (KDZERO+0x1000ull) /* gdt */
+#define CPU0MACH (KDZERO+0x2000ull) /* Mach for bootstrap processor (BSP) */
+#define CPU0END (KDZERO+0x12000ull) /* CPU0MACH + (MACHSIZE = 64 KiB = 0x10 000) */
/* MACHSIZE includes stack size */
-#define CPU0SP (KDZERO+0x22000ull)
+#define CPU0SP (KDZERO+0x12000ull)
/* 1 PD table has 512 entries
* each entry maps to a 2MB page
* 512 entries maps 1GiB and occupies 512*8 = 4096 bytes
*/
-#define PML4ADDR (KDZERO+0x23000ull)
-#define PDPADDR (KDZERO+0x24000ull)
-#define PD0ADDR (KDZERO+0x25000ull) /* KZERO=0 .. 1GiB */
-#define PT0ADDR (KDZERO+0x26000ull) /* KZERO=0 .. 2MiB */
-#define PT1ADDR (KDZERO+0x27000ull) /* 2MiB .. 4MiB */
-#define PT2ADDR (KDZERO+0x28000ull) /* 4MiB .. 6MiB */
-#define PT3ADDR (KDZERO+0x29000ull) /* 6MiB .. 8MiB */
+#define PML4ADDR (KDZERO+0x13000ull)
+#define PDPADDR (KDZERO+0x14000ull) /* KZERO=0 .. 512GiB */
+#define PD0ADDR (KDZERO+0x15000ull) /* KZERO=0 .. 1GiB */
+#define PT0ADDR (KDZERO+0x16000ull) /* KZERO=0 .. 2MiB */
+#define PT1ADDR (KDZERO+0x17000ull) /* 2MiB .. 4MiB */
+#define PT2ADDR (KDZERO+0x18000ull) /* 4MiB .. 6MiB */
+#define PT3ADDR (KDZERO+0x19000ull) /* 6MiB .. 8MiB */
/* fill with page tables until KTZERO */
/*
* Where configuration info is left for us by 9boot.
* (e.g. why parse the .ini file twice?).
- * There are 24064 bytes available at CONFADDR.
+ * Free memory until REBOOTADDR
*/
#define BOOTLINE ((char*)CONFADDR)
#define BOOTLINELEN 64
#define BOOTARGS ((char*)(CONFADDR+BOOTLINELEN))
-#define BOOTARGSLEN (0x6000-0x200-BOOTLINELEN)
+ /* 9front uses -0x200 to end on a page boundary */
+#define BOOTARGSLEN (4096-0x200-BOOTLINELEN)
/*
* known x86 segments (in GDT) and their selectors
--- a/os/pc64/memory.c
+++ b/os/pc64/memory.c
@@ -159,20 +159,16 @@
uintptr base, pa, len;
uchar *p;
- /*
- * Discover the memory bank information for conventional memory
- * (i.e. less than 640KB). The base is the first location after the
- * bootstrap processor MMU information and the limit is obtained from
- * the BIOS data area.
+ /* Reserve
+ * 0x000 - 0x3FF Real mode IVT
+ * 0x400 - 0x4FF BIOS data area (BDA)
+ * 0x1200 - 0x2000 BOOTARGS
*/
- base = PADDR(CPU0END);
- pa = convmemsize();
- if(base < pa)
- memmapadd(base, pa-base, MemRAM);
+ memmapadd(0, 2*4*KiB, MemRAM);
+ if(memmapalloc(0, 2*4*KiB, BY2PG, MemRAM) == -1){
+ print("lowraminit: could not memmapalloc BDA\n");
+ }
- /* Reserve BIOS tables */
- memmapadd(pa, 1*KB, MemReserved);
-
/* Allocate memory to be used for reboot code */
len=4*KiB /* sizeof(rebootcode) */;
memmapadd(PADDR(PGROUND((uintptr)REBOOTADDR)), len, MemRAM);
@@ -188,6 +184,20 @@
print("lowraminit: could not memmapalloc APBOOTSTRAP 0x%p len 0x%zd\n",
PADDR(PGROUND((uintptr)APBOOTSTRAP)), len);
}
+
+ /*
+ * Discover the memory bank information for conventional memory
+ * (i.e. less than 640KB). The base is the first location after the
+ * bootstrap processor MMU information and the limit is obtained from
+ * the BIOS data area.
+ */
+ base = PADDR(CPU0END);
+ pa = convmemsize();
+ if(base < pa)
+ memmapadd(base, pa-base, MemRAM);
+
+ /* Reserve BIOS tables */
+ memmapadd(pa, 1*KB, MemReserved);
/* Reserve EBDA */
if((pa = ebdaseg()) != 0)
--- a/os/pc64/mkfile
+++ b/os/pc64/mkfile
@@ -12,8 +12,8 @@
#INSTALLDIR=/$OBJTYPE
# must match mem.h
-REBOOTADDR=0x4000
-APBOOTSTRAP=0x5000
+REBOOTADDR=0x2000
+APBOOTSTRAP=0x3000
KTZERO=0x200000
#end configurable parameters