code: plan9front

Download patch

ref: 9ebe38c9602310d6c8404e1d8104a744c09f0215
parent: 90a09ca00c063457f86a14207ca63991b1f910c4
author: Aidan K. Wiggins <akw@oneiri.one>
date: Thu May 18 19:42:31 EDT 2023 

7l, 7c: Remove STLP(W), finish LDAXR(W)/STLXR(W).


--- a/sys/src/cmd/7c/7.out.h
+++ b/sys/src/cmd/7c/7.out.h
@@ -223,8 +223,8 @@
 	ASTXP,
 	ASTXPW,
 	ASTXRW,
-	ASTLP,
-	ASTLPW,
+	ASTLP,	/* not an instruction */
+	ASTLPW, /* kept for order */
 	ASTLR,
 	ASTLRB,
 	ASTLRH,
--- a/sys/src/cmd/7c/peep.c
+++ b/sys/src/cmd/7c/peep.c
@@ -76,7 +76,6 @@
 	case ASDIVW:
 	case ASTXPW:
 	case ASTXRW:
-	case ASTLPW:
 	case ASTLRW:
 	case ASTLXPW:
 	case ASTLXRW:
--- a/sys/src/cmd/7l/asmout.c
+++ b/sys/src/cmd/7l/asmout.c
@@ -1451,20 +1451,25 @@
 	switch(a){
 	case ALDAR:	return LDSTX(3,1,1,0,1) | 0x1F<<10;
 	case ALDARW:	return LDSTX(2,1,1,0,1) | 0x1F<<10;
-	case ALDARB:	return LDSTX(0,1,1,0,1) | 0x1F<<10;
 	case ALDARH:	return LDSTX(1,1,1,0,1) | 0x1F<<10;
+	case ALDARB:	return LDSTX(0,1,1,0,1) | 0x1F<<10;
+
 	case ALDAXP:	return LDSTX(3,0,1,1,1);
 	case ALDAXPW:	return LDSTX(2,0,1,1,1);
+
 	case ALDAXR:	return LDSTX(3,0,1,0,1) | 0x1F<<10;
-	case ALDAXRW:	return LDSTX(2,1,1,0,1) | 0x1F<<10;
-	case ALDAXRB:	return LDSTX(0,0,1,0,1) | 0x1F<<10;
+	case ALDAXRW:	return LDSTX(2,0,1,0,1) | 0x1F<<10;
 	case ALDAXRH:	return LDSTX(1,0,1,0,1) | 0x1F<<10;
-	case ALDXR:		return LDSTX(3,0,1,0,0) | 0x1F<<10;
-	case ALDXRB:		return LDSTX(0,0,1,0,0) | 0x1F<<10;
-	case ALDXRH:		return LDSTX(1,0,1,0,0) | 0x1F<<10;
-	case ALDXRW:		return LDSTX(2,0,1,0,0) | 0x1F<<10;
-	case ALDXP:		return LDSTX(3,0,1,1,0);
-	case ALDXPW:		return LDSTX(2,0,1,1,0);
+	case ALDAXRB:	return LDSTX(0,0,1,0,1) | 0x1F<<10;
+
+	case ALDXR:	return LDSTX(3,0,1,0,0) | 0x1F<<10;
+	case ALDXRW:	return LDSTX(2,0,1,0,0) | 0x1F<<10;
+	case ALDXRH:	return LDSTX(1,0,1,0,0) | 0x1F<<10;
+	case ALDXRB:	return LDSTX(0,0,1,0,0) | 0x1F<<10;
+
+	case ALDXP:	return LDSTX(3,0,1,1,0);
+	case ALDXPW:	return LDSTX(2,0,1,1,0);
+
 	case AMOVNP:	return S64 | 0<<30 | 5<<27 | 0<<26 | 0<<23 | 1<<22;
 	case AMOVNPW:	return S32 | 0<<30 | 5<<27 | 0<<26 | 0<<23 | 1<<22;
 	}
@@ -1477,23 +1482,26 @@
 {
 	switch(a){
 	case ASTLR:		return LDSTX(3,1,0,0,1) | 0x1F<<10;
-	case ASTLRB:		return LDSTX(0,1,0,0,1) | 0x1F<<10;
-	case ASTLRH:		return LDSTX(1,1,0,0,1) | 0x1F<<10;
-	case ASTLP:		return LDSTX(3,0,0,1,1);
-	case ASTLPW:		return LDSTX(2,0,0,1,1);
 	case ASTLRW:		return LDSTX(2,1,0,0,1) | 0x1F<<10;
-	case ASTLXP:		return LDSTX(2,0,0,1,1);
-	case ASTLXPW:		return LDSTX(3,0,0,1,1);
+	case ASTLRH:		return LDSTX(1,1,0,0,1) | 0x1F<<10;
+	case ASTLRB:		return LDSTX(0,1,0,0,1) | 0x1F<<10;
+
+	case ASTLXP:		return LDSTX(3,0,0,1,1);
+	case ASTLXPW:		return LDSTX(2,0,0,1,1);
+
 	case ASTLXR:		return LDSTX(3,0,0,0,1) | 0x1F<<10;
-	case ASTLXRB:		return LDSTX(0,0,0,0,1) | 0x1F<<10;
-	case ASTLXRH:		return LDSTX(1,0,0,0,1) | 0x1F<<10;
 	case ASTLXRW:		return LDSTX(2,0,0,0,1) | 0x1F<<10;
+	case ASTLXRH:		return LDSTX(1,0,0,0,1) | 0x1F<<10;
+	case ASTLXRB:		return LDSTX(0,0,0,0,1) | 0x1F<<10;
+
 	case ASTXR:		return LDSTX(3,0,0,0,0) | 0x1F<<10;
-	case ASTXRB:		return LDSTX(0,0,0,0,0) | 0x1F<<10;
+	case ASTXRW:		return LDSTX(2,0,0,0,0) | 0x1F<<10;
 	case ASTXRH:		return LDSTX(1,0,0,0,0) | 0x1F<<10;
+	case ASTXRB:		return LDSTX(0,0,0,0,0) | 0x1F<<10;
+
 	case ASTXP:		return LDSTX(3,0,0,1,0);
 	case ASTXPW:		return LDSTX(2,0,0,1,0);
-	case ASTXRW:		return LDSTX(2,0,0,0,0) | 0x1F<<10;
+
 	case AMOVNP:	return S64 | 0<<30 | 5<<27 | 0<<26 | 0<<23 | 1<<22;
 	case AMOVNPW:	return S32 | 0<<30 | 5<<27 | 0<<26 | 0<<23 | 1<<22;
 	}
--- a/sys/src/cmd/7l/optab.c
+++ b/sys/src/cmd/7l/optab.c
@@ -449,9 +449,14 @@
 	{ AHINT,		C_LCON,	C_NONE,	C_NONE,		52, 4, 0 },
 
 	{ ALDXR,		C_ZOREG,	C_NONE,	C_REG,		58, 4, 0 },
+	{ ALDAXR,		C_ZOREG,	C_NONE, C_REG,		58, 4, 0 },
 	{ ALDXP,		C_ZOREG,	C_REG,	C_REG,		58, 4, 0 },
+	{ ALDAXP,		C_ZOREG,	C_REG,	C_REG,		58, 4, 0 },
+
 	{ ASTXR,		C_REG,	C_REG,	C_ZOREG,		59, 4, 0 },
-	{ ASTXP,		C_REG, C_REG,	C_ZOREG,		59, 4, 0 },
+	{ ASTLXR,		C_REG,	C_REG,	C_ZOREG,		59, 4, 0 },
+	{ ASTXP,		C_REG,	C_REG,	C_ZOREG,		59, 4, 0 },
+	{ ASTLXP,		C_REG,	C_REG,	C_ZOREG,		59, 4, 0 },
 
 	{ AAESD,	C_VREG,	C_NONE,	C_VREG,	29, 4, 0 },
 	{ ASHA1C,	C_VREG,	C_REG,	C_VREG,	1, 4, 0 },
--- a/sys/src/cmd/7l/span.c
+++ b/sys/src/cmd/7l/span.c
@@ -1325,20 +1325,36 @@
 			break;
 
 		case ALDXR:
-			oprange[ALDXRB] = t;
-			oprange[ALDXRH] = t;
 			oprange[ALDXRW] = t;
+			oprange[ALDXRH] = t;
+			oprange[ALDXRB] = t;
 			break;
+		case ALDAXR:
+			oprange[ALDAXRW] = t;
+			oprange[ALDAXRH] = t;
+			oprange[ALDAXRB] = t;
+			break;
 		case ALDXP:
 			oprange[ALDXPW] = t;
 			break;
+		case ALDAXP:
+			oprange[ALDAXPW] = t;
+			break;
 		case ASTXR:
-			oprange[ASTXRB] = t;
-			oprange[ASTXRH] = t;
 			oprange[ASTXRW] = t;
+			oprange[ASTXRH] = t;
+			oprange[ASTXRB] = t;
 			break;
+		case ASTLXR:
+			oprange[ASTLXRW] = t;
+			oprange[ASTLXRH] = t;
+			oprange[ASTLXRB] = t;
+			break;
 		case ASTXP:
 			oprange[ASTXPW] = t;
+			break;
+		case ASTLXP:
+			oprange[ASTLXPW] = t;
 			break;
 
 		case AAESD: