ref: f43c301827e7a22faddc50cc1c41d16c6fa3cf38
parent: 6b5d2ac468490a417e2dc36d13662b021d360200
author: mia soweli <inbox@tachibana-labs.org>
date: Mon Jun 24 16:22:31 EDT 2024
9/pc: Remove unused lm78 driver This seems to have been around but not compiled since the third edition. Remove it and the accompanying SMBus machinery that is only used for this driver.
--- a/sys/src/9/pc/devlm78.c
+++ /dev/null
@@ -1,347 +1,0 @@
-#include "u.h"
-#include "../port/lib.h"
-#include "mem.h"
-#include "dat.h"
-#include "fns.h"
-#include "io.h"
-#include "ureg.h"
-#include "../port/pci.h"
-#include "../port/error.h"
-
-/* this driver doesn't implement the management interrupts. we
- * leave the LM78 interrupts set to whatever the BIOS did. we do
- * allow reading and writing the the readouts and alarm values.
- * Read(2)ing or write(2)ing at offset 0x0-0x1f, is
- * equivalent to reading or writing lm78 registers 0x20-0x3f.
- */
-enum
-{- /* address of chip on serial interface */
- Serialaddr= 0x2d,
-
- /* parallel access registers */
- Rpaddr= 0x5,
- Bbusy= (1<<7),
- Rpdata= 0x6,
-
- /* internal register addresses */
- Rconfig= 0x40,
- Bstart= (1<<0),
- Bsmiena= (1<<1),
- Birqena= (1<<2),
- Bintclr= (1<<3),
- Breset= (1<<4),
- Bnmi= (1<<5), /* if set, use nmi, else irq */
- Bpowbypass= (1<<6),
- Binit= (1<<7),
- Ristat1= 0x41,
- Ristat2= 0x42,
- Rsmimask1= 0x43,
- Rsmimask2= 0x44,
- Rnmimask1= 0x45,
- Rnmimask2= 0x46,
- Rvidfan= 0x47, /* set fan counter, and read voltage level */
- Mvid= 0x0f,
- Mfan= 0xf0,
- Raddr= 0x48, /* address used on serial bus */
- Rresetid= 0x49, /* chip reset and ID register */
- Rpost= 0x00, /* start of post ram */
- Rvalue= 0x20, /* start of value ram */
-
- VRsize= 0x20, /* size of value ram */
-};
-
-enum
-{- Qdir,
- Qlm78vram,
-};
-
-static Dirtab lm78dir[] = {- ".", { Qdir, 0, QTDIR}, 0, 0555,- "lm78vram", { Qlm78vram, 0 }, 0, 0444,-};
-
-/* interface type */
-enum
-{- None= 0,
- Smbus,
- Parallel,
-};
-
-static struct {- QLock;
- int probed;
- int ifc; /* which interface is connected */
- SMBus *smbus; /* serial interface */
- int port; /* parallel interface */
-} lm78;
-
-extern SMBus* piix4smbus(void);
-
-/* wait for device to become quiescent and then set the */
-/* register address */
-static void
-setreg(int reg)
-{- int tries;
-
- for(tries = 0; tries < 1000000; tries++)
- if((inb(lm78.port+Rpaddr) & Bbusy) == 0){- outb(lm78.port+Rpaddr, reg);
- return;
- }
- error("lm78 broken");-}
-
-/* routines that actually touch the device */
-static void
-lm78wrreg(int reg, uchar val)
-{- if(waserror()){- qunlock(&lm78);
- nexterror();
- }
- qlock(&lm78);
-
- switch(lm78.ifc){- case Smbus:
- lm78.smbus->transact(lm78.smbus, SMBbytewrite, Serialaddr, reg, &val);
- break;
- case Parallel:
- setreg(reg);
- outb(lm78.port+Rpdata, val);
- break;
- default:
- error(Enodev);
- break;
- }
-
- qunlock(&lm78);
- poperror();
-}
-
-static int
-lm78rdreg(int reg)
-{- uchar val;
-
- if(waserror()){- qunlock(&lm78);
- nexterror();
- }
- qlock(&lm78);
-
- switch(lm78.ifc){- case Smbus:
- lm78.smbus->transact(lm78.smbus, SMBsend, Serialaddr, reg, nil);
- lm78.smbus->transact(lm78.smbus, SMBrecv, Serialaddr, 0, &val);
- break;
- case Parallel:
- setreg(reg);
- val = inb(lm78.port+Rpdata);
- break;
- default:
- error(Enodev);
- break;
- }
-
- qunlock(&lm78);
- poperror();
- return val;
-}
-
-/* start the chip monitoring but don't change any smi
- * interrupts and/or alarms that the BIOS may have set up.
- * this isn't locked because it's thought to be idempotent
- */
-static void
-lm78enable(void)
-{- uchar config;
-
- if(lm78.ifc == None)
- error(Enodev);
-
- if(lm78.probed == 0){- /* make sure its really there */
- if(lm78rdreg(Raddr) != Serialaddr){- lm78.ifc = None;
- error(Enodev);
- } else {- /* start the sampling */
- config = lm78rdreg(Rconfig);
- config = (config | Bstart) & ~(Bintclr|Binit);
- lm78wrreg(Rconfig, config);
-pprint("Rvidfan %2.2ux\n", lm78rdreg(Rconfig), lm78rdreg(Rvidfan));- }
- lm78.probed = 1;
- }
-}
-
-enum
-{- IntelVendID= 0x8086,
- PiixID= 0x122E,
- Piix3ID= 0x7000,
-
- Piix4PMID= 0x7113, /* PIIX4 power management function */
-
- PCSC= 0x78, /* programmable chip select control register */
- PCSC8bytes= 0x01,
-};
-
-/* figure out what kind of interface we could have */
-void
-lm78reset(void)
-{- int pcs;
- Pcidev *p;
-
- lm78.ifc = None;
- p = nil;
- while((p = pcimatch(p, IntelVendID, 0)) != nil){- switch(p->did){- /* these bridges use the PCSC to map the lm78 into port space. */
- /* for this case the lm78's CS# select is connected to the PIIX's */
- /* PCS# output and the bottom 3 bits of address are passed to the */
- /* LM78's A0-A2 inputs. */
- case PiixID:
- case Piix3ID:
- pcs = pcicfgr16(p, PCSC);
- if(pcs & 3) {- /* already enabled */
- lm78.port = pcs & ~3;
- lm78.ifc = Parallel;
- return;
- }
-
- /* enable the chip, use default address 0x50 */
- pcicfgw16(p, PCSC, 0x50|PCSC8bytes);
- pcs = pcicfgr16(p, PCSC);
- lm78.port = pcs & ~3;
- lm78.ifc = Parallel;
- return;
-
- /* this bridge puts the lm78's serial interface on the smbus */
- case Piix4PMID:
- lm78.smbus = piix4smbus();
- if(lm78.smbus == nil)
- continue;
- print("found piix4 smbus, base %lud\n", lm78.smbus->base);- lm78.ifc = Smbus;
- return;
- }
- }
-}
-
-Walkqid *
-lm78walk(Chan* c, Chan *nc, char** name, int nname)
-{- return devwalk(c, nc, name, nname, lm78dir, nelem(lm78dir), devgen);
-}
-
-static int
-lm78stat(Chan* c, uchar* dp, int n)
-{- return devstat(c, dp, n, lm78dir, nelem(lm78dir), devgen);
-}
-
-static Chan*
-lm78open(Chan* c, int omode)
-{- return devopen(c, omode, lm78dir, nelem(lm78dir), devgen);
-}
-
-static void
-lm78close(Chan*)
-{-}
-
-enum
-{- Linelen= 25,
-};
-
-static long
-lm78read(Chan *c, void *a, long n, vlong offset)
-{- uchar *va = a;
- int off, e;
-
- off = offset;
-
- switch((ulong)c->qid.path){- case Qdir:
- return devdirread(c, a, n, lm78dir, nelem(lm78dir), devgen);
-
- case Qlm78vram:
- if(off >= VRsize)
- return 0;
- e = off + n;
- if(e > VRsize)
- e = VRsize;
- for(; off < e; off++)
- *va++ = lm78rdreg(Rvalue+off);
- return (int)(va - (uchar*)a);
- }
- return 0;
-}
-
-static long
-lm78write(Chan *c, void *a, long n, vlong offset)
-{- uchar *va = a;
- int off, e;
-
- off = offset;
-
- switch((ulong)c->qid.path){- default:
- error(Eperm);
-
- case Qlm78vram:
- if(off >= VRsize)
- return 0;
- e = off + n;
- if(e > VRsize)
- e = VRsize;
- for(; off < e; off++)
- lm78wrreg(Rvalue+off, *va++);
- return va - (uchar*)a;
- }
- return 0;
-}
-
-extern Dev lm78devtab;
-
-static Chan*
-lm78attach(char* spec)
-{- lm78enable();
-
- return devattach(lm78devtab.dc, spec);
-}
-
-Dev lm78devtab = {- 'T',
- "lm78",
-
- lm78reset,
- devinit,
- devshutdown,
- lm78attach,
- lm78walk,
- lm78stat,
- lm78open,
- devcreate,
- lm78close,
- lm78read,
- devbread,
- lm78write,
- devbwrite,
- devremove,
- devwstat,
-};
-
--- a/sys/src/9/pc/io.h
+++ b/sys/src/9/pc/io.h
@@ -79,32 +79,6 @@
#define BUSUNKNOWN (-1)
-/* SMBus transactions */
-enum
-{- SMBquick, /* sends address only */
-
- /* write */
- SMBsend, /* sends address and cmd */
- SMBbytewrite, /* sends address and cmd and 1 byte */
- SMBwordwrite, /* sends address and cmd and 2 bytes */
-
- /* read */
- SMBrecv, /* sends address, recvs 1 byte */
- SMBbyteread, /* sends address and cmd, recv's byte */
- SMBwordread, /* sends address and cmd, recv's 2 bytes */
-};
-
-typedef struct SMBus SMBus;
-struct SMBus {- QLock; /* mutex */
- Rendez r; /* rendezvous point for completion interrupts */
- void *arg; /* implementation dependent */
- ulong base; /* port or memory base of smbus */
- int busy;
- void (*transact)(SMBus*, int, int, int, uchar*);
-};
-
/*
* PCMCIA support code.
*/
--- a/sys/src/9/pc/piix4smbus.c
+++ /dev/null
@@ -1,216 +1,0 @@
-#include "u.h"
-#include "../port/lib.h"
-#include "mem.h"
-#include "dat.h"
-#include "fns.h"
-#include "io.h"
-#include "../port/pci.h"
-
-/*
- * SMBus support for the PIIX4
- */
-enum
-{- IntelVendID= 0x8086,
- Piix4PMID= 0x7113, /* PIIX4 power management function */
-
- /* SMBus configuration registers (function 3) */
- SMBbase= 0x90, /* 4 byte base address (bit 0 == 1, bit 3:1 == 0) */
- SMBconfig= 0xd2,
- SMBintrselect= (7<<1),
- SMIenable= (0<<1), /* interrupts sent to SMI# */
- IRQ9enable= (4<<1), /* interrupts sent to IRQ9 */
- SMBenable= (1<<0), /* 1 enables */
-
- /* SMBus IO space registers */
- Hoststatus= 0x0, /* (writing 1 bits reset the interrupt bits) */
- Failed= (1<<4), /* transaction terminated by KILL */
- Bus_error= (1<<3), /* transaction collision */
- Dev_error= (1<<2), /* device error interrupt */
- Host_complete= (1<<1), /* host command completion interrupt */
- Host_busy= (1<<0), /* */
- Slavestatus= 0x1, /* (writing 1 bits reset) */
- Alert_sts= (1<<5), /* someone asserted SMBALERT# */
- Shdw2_sts= (1<<4), /* slave accessed shadow 2 port */
- Shdw1_sts= (1<<3), /* slave accessed shadow 1 port */
- Slv_sts= (1<<2), /* slave accessed shadow 1 port */
- Slv_bsy= (1<<0),
- Hostcontrol= 0x2,
- Start= (1<<6), /* start execution */
- Cmd_prot= (7<<2), /* command protocol mask */
- Quick= (0<<2), /* address only */
- Byte= (1<<2), /* address + cmd */
- ByteData= (2<<2), /* address + cmd + data */
- WordData= (3<<2), /* address + cmd + data + data */
- Kill= (1<<1), /* abort in progress command */
- Ienable= (1<<0), /* enable completion interrupts */
- Hostcommand= 0x3,
- Hostaddress= 0x4,
- AddressMask= (0x7f<<1), /* target address */
- Read= (1<<0), /* 1 == read, 0 == write */
- Hostdata0= 0x5,
- Hostdata1= 0x6,
- Blockdata= 0x7,
- Slavecontrol= 0x8,
- Alert_en= (1<<3), /* enable inter on SMBALERT# */
- Shdw2_en= (1<<2), /* enable inter on external shadow 2 access */
- Shdw1_en= (1<<1), /* enable inter on external shadow 1 access */
- Slv_en= (1<<0), /* enable inter on access of host ctlr slave port */
- Shadowcommand= 0x9,
- Slaveevent= 0xa,
- Slavedata= 0xc,
-};
-
-static struct
-{- int rw;
- int cmd;
- int len;
- int proto;
-} proto[] =
-{- [SMBquick] { 0, 0, 0, Quick },- [SMBsend] { 0, 1, 0, Byte },- [SMBbytewrite] { 0, 1, 1, ByteData },- [SMBwordwrite] { 0, 1, 2, WordData },- [SMBrecv] { Read, 0, 1, Byte },- [SMBbyteread] { Read, 1, 1, ByteData },- [SMBwordread] { Read, 1, 2, WordData },-};
-
-static void
-transact(SMBus *s, int type, int addr, int cmd, uchar *data)
-{- int tries, status;
- char err[256];
-
- if(type < 0 || type > nelem(proto))
- panic("piix4smbus: illegal transaction type %d", type);-
- if(waserror()){- qunlock(s);
- nexterror();
- }
- qlock(s);
-
- /* wait a while for the host interface to be available */
- for(tries = 0; tries < 1000000; tries++){- if((inb(s->base+Hoststatus) & Host_busy) == 0)
- break;
- sched();
- }
- if(tries >= 1000000){- /* try aborting current transaction */
- outb(s->base+Hostcontrol, Kill);
- for(tries = 0; tries < 1000000; tries++){- if((inb(s->base+Hoststatus) & Host_busy) == 0)
- break;
- sched();
- }
- if(tries >= 1000000){- snprint(err, sizeof(err), "SMBus jammed: %2.2ux", inb(s->base+Hoststatus));
- error(err);
- }
- }
-
- /* set up for transaction */
- outb(s->base+Hostaddress, (addr<<1)|proto[type].rw);
- if(proto[type].cmd)
- outb(s->base+Hostcommand, cmd);
- if(proto[type].rw != Read){- switch(proto[type].len){- case 2:
- outb(s->base+Hostdata1, data[1]);
- /* fall through */
- case 1:
- outb(s->base+Hostdata0, data[0]);
- break;
- }
- }
-
-
- /* reset the completion/error bits and start transaction */
- outb(s->base+Hoststatus, Failed|Bus_error|Dev_error|Host_complete);
- outb(s->base+Hostcontrol, Start|proto[type].proto);
-
- /* wait for completion */
- status = 0;
- for(tries = 0; tries < 1000000; tries++){- status = inb(s->base+Hoststatus);
- if(status & (Failed|Bus_error|Dev_error|Host_complete))
- break;
- sched();
- }
- if((status & Host_complete) == 0){- snprint(err, sizeof(err), "SMBus request failed: %2.2ux", status);
- error(err);
- }
-
- /* get results */
- if(proto[type].rw == Read){- switch(proto[type].len){- case 2:
- data[1] = inb(s->base+Hostdata1);
- /* fall through */
- case 1:
- data[0] = inb(s->base+Hostdata0);
- break;
- }
- }
- qunlock(s);
- poperror();
-}
-
-static SMBus smbusproto =
-{- .transact = transact,
-};
-
-/*
- * return 0 if this is a piix4 with an smbus interface
- */
-SMBus*
-piix4smbus(void)
-{- Pcidev *p;
- static SMBus *s;
-
- if(s != nil)
- return s;
-
- p = pcimatch(nil, IntelVendID, Piix4PMID);
- if(p == nil)
- return nil;
-
- s = malloc(sizeof(*s));
- if(s == nil)
- panic("piix4smbus: no memory for SMBus");- memmove(s, &smbusproto, sizeof(*s));
- s->arg = p;
-
- /* disable the smbus */
- pcicfgw8(p, SMBconfig, IRQ9enable|0);
-
- /* see if bios gave us a viable port space */
- s->base = pcicfgr32(p, SMBbase) & ~1;
-print("SMB base from bios is 0x%lux\n", s->base);- if(ioalloc(s->base, 0xd, 0, "piix4smbus") < 0){- s->base = ioalloc(-1, 0xd, 2, "piix4smbus");
- if(s->base < 0){- free(s);
- print("piix4smbus: can't allocate io port\n");- return nil;
- }
-print("SMB base ialloc is 0x%lux\n", s->base);- pcicfgw32(p, SMBbase, s->base|1);
- }
-
- /* disable SMBus interrupts, abort any transaction in progress */
- outb(s->base+Hostcontrol, Kill);
- outb(s->base+Slavecontrol, 0);
-
- /* enable the smbus */
- pcicfgw8(p, SMBconfig, IRQ9enable|SMBenable);
-
- return s;
-}