ref: 09d11c64e5014a64dbc7b807899b3dd2581fe26f
dir: /os/rpcg/tlb.s/
#include "mem.h" #define MB (1024*1024) /* * TLB prototype entries, loaded once-for-all at startup, * remaining unchanged thereafter. * Limit the table to at most 8 entries to ensure * it works on the 823 (other 8xx processors allow up to 32 TLB entries). */ #define TLBE(epn,rpn,twc) WORD $(epn); WORD $(twc); WORD $(rpn) TEXT tlbtab(SB), $-4 /* epn, rpn, twc */ TLBE(KZERO|PHYSDRAM|TLBVALID, PHYSDRAM|PTEWRITE|PTELPS|PTESH|PTEVALID, PTE8MB|/*PTEWT|*/PTEVALID) /* DRAM, 8M */ TLBE(KZERO|(PHYSDRAM+8*MB)|TLBVALID, (PHYSDRAM+8*MB)|PTEWRITE|PTELPS|PTESH|PTEVALID, PTE8MB|PTEVALID) /* DRAM, 8M */ TLBE(KZERO|PHYSBCSR|TLBVALID, PHYSBCSR|PTEWRITE|PTESH|PTECI|PTEVALID, PTE4K|PTEWT|PTEVALID) /* Board CSR, 4K */ TLBE(KZERO|PHYSIMM|TLBVALID, PHYSIMM|PTEWRITE|PTELPS|PTESH|PTECI|PTEVALID, PTE4K|PTEWT|PTEVALID) /* IMMR, 16K */ TLBE(KZERO|PHYSFLASH|TLBVALID, PHYSFLASH|PTEWRITE|PTELPS|PTESH|PTECI|PTEVALID, PTE8MB|PTEWT|PTEVALID) /* Flash, 8M */ TLBE(KZERO|PHYSPCMCIA|TLBVALID, PHYSPCMCIA|PTEWRITE|PTELPS|PTESH|PTECI|PTEVALID, PTE8MB|PTEWT|PTEG|PTEVALID) /* PCMCIA, 8M */ TLBE(KZERO|PHYSNVRAM|TLBVALID, PHYSNVRAM|PTEWRITE|PTELPS|PTESH|PTECI|PTEVALID, PTE512K|PTEWT|PTEG|PTEVALID) /* NVRAM, 512K */ TEXT tlbtabe(SB), $-4 RETURN